The present invention is related to circuits and methods for implementing transistor devices, and more particularly to circuits and methods for reducing mismatch across transistor devices.
A typical semiconductor device includes a large number of transistors configured to perform one or more functions germane to the operation of the semiconductor device. In some cases, operation of the semiconductor device may be limited due to mismatches between transistors incorporated on the semiconductor device. Such mismatches include a variance in threshold voltage (VT), length (L) and width (W) across transistors. As some examples, a mismatch in transistors used in a current mirror or differential pair can lead to subtle operational differences that may in some cases be fundamental to proper operation.
FIGS. 1a-1b show an exemplary current mirror 100 and an exemplary differential input pair 150 where a mismatch in transistors results in an undesirable operational variance. Current mirror 100 includes a PMOS transistor 102 and two resistors 104, 106. In addition, current mirror 100 includes three NMOS transistors 108, 110, 112. In operation, a voltage (Vin) 114 is applied to the gate of PMOS transistor 102. This causes PMOS transistor 102 to turn on such that the drain of PMOS transistor 102 exhibits a voltage near that of the source of PMOS transistor 102. The voltage at the drain of PMOS transistor 102 is applied to the drain of NMOS transistor 108, and the gates of NMOS transistors 108, 110, 112. This results in a reference current 116 (Ir) traversing PMOS transistor 102 and NMOS transistor 108. Currents 118, 120 (Ia, Ib) proportional to reference current 116 traverse NMOS transistor 110 and NMOS transistor 112, respectively. The following equations describe proportional currents 118, 120:Ia=k1*Ir; andIb=k2*Ir. The constant k1 is the ratio of the area of NMOS transistor 108 to NMOS transistor 110, and the constant k2 is the ratio of the area of NMOS transistor 108 to NMOS transistor 112. As can be readily appreciated, any variance in the width or length in any of NMOS transistor 108, NMOS transistor 110 or NMOS transistor 112 has a direct impact on the relationship of each of proportional currents 118, 120.
Turning to FIG. 1b, differential input pair 150 is depicted. Differential input pair 150 includes an NMOS transistor 152 and an NMOS transistor 154. The drain of NMOS transistor 152 is electrically coupled to a resistor 156 and a positive output 164 (Vout+), and the drain of NMOS transistor 154 is electrically coupled to a resistor 158 and to a negative output 160 (Vout−). The gate of NMOS transistor 152 is electrically coupled to a positive input 162 (Vin+), and the gate of NMOS transistor 154 is electrically coupled to a negative input 160 (Vin−). The source of each of NMOS transistors 152, 154 are electrically coupled to each other, and to a current source 168. Ideally, when positive input 162 equals negative input 164, the same current (i.e., ½ current source 168) should traverse each of resistors 156, 158 such that positive output 164 equals negative output 166. However, where the threshold voltage of NMOS transistor 152 is different from that of NMOS transistor 154, positive output 164 will not equal negative output 166 when positive input 162 equals negative input 160. Thus, a variance in threshold voltage across transistors has a direct and undesirable impact on circuit performance.
In some cases variance in threshold voltage, width and length across transistors exhibits an absolute maximum. Thus, an increase in area of a transistor minimizes the impact of any length or width variance. This is, however, contrary to trends in the semiconductor area where reduced transistor sizes are desired. Indeed, as transistor sizes continue to decrease, the impact of variances is becoming more and more significant. Some attempts to reduce the variance have involved decreasing the resolution of semiconductor manufacturing equipment to further limit any variance. While such attempts have generally been successful, a certain variance across transistors is still expected.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for implementing transistors.